Cypress Semiconductor /psoc63 /CPUSS /CM0_CTL

Processor debug access control: ‘0’: Access. ‘1’: Stall access.

This field is used to stall/delay debug accesses. This is useful to protect execution of code that needs to be protected from debug accesses.

Processor enable: ‘0’: Disabled. Processor clock is turned off and reset is activated. After SW clears this field to ‘0’, HW automatically sets this field to ‘1’. This effectively results in a CM0+ reset, followed by a CM0+ warm boot. ‘1’: Enabled. Note: The intent is that this bit is modified only through an external probe or by the CM4 while the CM0+ is in Sleep or DeepSleep power mode. If this field is cleared to ‘0’ by the CM0+ itself, it should be done under controlled conditions (such that undesirable side effects can be prevented).

Note: The CM0+ CPU has a AIRCR.SYSRESETREQ register field that allows the CM0+ to reset the complete device (ENABLED only disables/enables the CM0+), resulting in a warm boot. This CPU register field has similar ‘built-in protection’ as this CM0_CTL register to prevent accidental system writes (the upper 16-bits of the register need to be written with a 0x05fa key value; see CPU user manual for more details).

Register key (to prevent accidental writes).

• Should be written with a 0x05fa key value for the write to take effect.
• Always reads as 0xfa05.